The speeds of metal-oxide-semiconductor (MOS) transistors are closely related to the drive currents of the MOS transistors, which drive currents are further closely related to the mobility of charges. For example, NMOS transistors have higher drive currents when the electron mobility in their channel regions is high, while PMOS transistors have higher drive currents when the hole mobility in their channel regions is high.
Germanium is a commonly known semiconductor material. The electron mobility and hole mobility of germanium are greater than that of silicon, which is the most commonly used semiconductor material in the formation of integrated circuits. Hence, germanium is an excellent material for forming integrated circuits. However, in the past, silicon gained more popularity since its oxide (silicon oxide) is readily usable in the gate dielectrics of MOS transistors. The gate dielectrics of the MOS transistors can be conveniently formed by thermally oxidizing silicon substrates. The oxide of germanium, on the other hand, is soluble in water, and hence is not suitable for the formation of gate dielectrics.
With the use of high-k dielectric materials in the gate dielectrics of MOS transistors, however, the convenience provided by the silicon oxide is no longer a big advantage, and hence germanium is reexamined for use in integrated circuits.
In addition to germanium, compound semiconductor materials of group III and group V elements (referred to as III-V compound semiconductors hereinafter) are also good candidates for forming NMOS devices for their high electron mobility.
A challenge faced by the semiconductor industry is that it is difficult to form germanium films with high germanium concentrations or pure germanium films, or III-V compound semiconductor films. Particularly, it is difficult to form high-concentration germanium films with low defect densities and great thicknesses. Previous research has revealed that when a silicon germanium film is epitaxially grown from a blank silicon wafer, the critical thickness of the silicon germanium film reduces with the increase in the percentage of germanium in the silicon germanium film, wherein the critical thickness is the maximum thickness the silicon germanium film can reach without being relaxed. When relaxation occurs, the lattice structure will be broken, and defects will be generated. For example, when formed on blank silicon wafers, the critical thickness of a silicon germanium film having a 20 percent germanium percentage may be about 10 nm to about 20 nm. To make things worse, when the germanium percentage increases to 40, 60, and 80 percent, the critical thicknesses are reduced to about 6-8 nm, 4-5 nm, and 2-3 nm, respectively. When the thickness of germanium films exceeds the critical thickness, the defects may reach as high as about 1×108/cm2. Accordingly, it is not feasible to form germanium films on blank silicon wafers for the purpose of forming MOS transistors, particularly fin field-effect transistors (FinFETs).
Previous research has disclosed methods for forming germanium regions from recesses between shallow trench isolation (STI) regions 4. FIG. 1 illustrates a conventional structure. STI regions 4 are formed in silicon substrate 2. Recesses are formed in silicon substrate 2 between STI regions 4, followed by growing germanium regions 6 in the recesses. The defect density of germanium regions 6 formed using this method is much lower than the defect density of germanium films grown on blank silicon substrates, sometimes by two orders. However, undesirable facets 8 may be formed by this formation method. On the other hand, the defect density is still high for forming high-performance MOS transistors.